In the semiconductor manufacturing industry, the size of features etched on substrates, such as semiconductor wafers, continues to decrease and transistor structures are becomes increasingly complex. For example, there is a growing trend of forming a chain of transistors vertically instead of laterally, as is the case in vertical NAND memory structures. These vertical structures come with their own unique challenges because very high aspect ratio holes must be made in order to make contacts or deep trenches so that the infrastructure for electrical pathways can be laid.
The etching of these high aspect ratio holes calls for the use of high ion energies in an abundant supply (ion flux). It is important that the holes do not bend or twist while etching and that the holes maintain consistency even when the holes become deeper without significant loss of etch rate. Solutions that are typically employed have several problems. First, existing solutions often apply frequencies to the same driven electrode closely couples ion energies and ion flux by influencing the plasma sheath. As a practical problem coupling all frequencies to the same driven electrode requires higher and higher low frequency power (responsible for ion energies) when higher flux (higher VHF) is required. The second problem with existing technologies is that the thermal burden on the transmission lines to the chamber and wafer carrying substrate is excessive.
Therefore, the inventors have provided methods and apparatus for plasma processing that decouple the ion energies and the ion flux and that reduce the thermal burden on transmission lines in plasma processing.